Solid-state drives (SSD) or other memory devices based on arrayed semiconductors have become very popular, but have only recently been produced with compression capability. Compression can result in significant reduction of write traffic to non-volatile memory (NVM) from a host device. The reduction in NVM writes causes corresponding reduction in the write amplification, which implies better performance, reliability, wear-leveling and less power consumption. Recovered area of SSD's can be exposed to the host device, effectively lowering the price per gigabyte of the SSD's
Based on desired bandwidth and process speeds, however, choosing a compression ratio presents challenges. With choice of a sufficiently high compression ratio, current LZ77-based algorithms considered best for implementation (e.g., LZ4, LZFX, LZSS, Snappy) are very costly, requiring in excess of three million gates. The tradeoffs between smaller area designs with less circuitry and good performance is a significant challenge. What is needed, therefore, is a less expensive compression/decompression design and methodology that meets favorable compression rations, bandwidth and speed.